Intel CONTROLLERS 413808 - Manual (Page 332)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
332 Order Number: 317805-001US
3.17.43 ATU Interrupt Mask Register - ATUIMR
The ATU Interrupt Mask Register contains the control bit to enable and disable
interrupts generated by the ATU.
Table 183. ATU Interrupt Mask Register - ATUIMR
Bit Default Description
31:29 0 Reserved
28 0 Slot Power Message Received Interrupt Mask - When ‘1’ the interrupt is masked.
27 0
Reserved
Note: The PME interrupt is masked in the “PCI Express Root Control Register - PE_RCR” on page 353
26 0 Hot-Plug Message Received Interrupt Mask - When ‘1’ the interrupt is masked
25 0 Inbound Vendor Message Received Interrupt Mask - When ‘1’ the interrupt is masked
24 0
Reserved
Note: The ATUBIST interrupt is masked by the BIST interrupt enable in the ATUCR register.
23:19 0 Reserved
18 0 ATU Configuration Write Mask - When ‘1’ the interrupt is masked.
17 0 VPD Address Register Updated Mask- When ‘1’ the interrupt is masked
16 0 Power State Transition Mask - When ‘1’ the interrupt is masked
15:14 0 Reserved
13 0 Halt on Error Interrupt Mask - When ‘1’ the interrupt is masked.
12 0 Root System Error Interrupt Mask - When ‘1’ the interrupt is masked
11 0 Reserved
10 0
Reserved
Note: ATUISR[10] is controlled by the “PCI Interface Error Mask - PIE_MSK” register.
09 0 Correctable Error Logged Interrupt Mask - When ‘1’ the interrupt is masked
08 0 Uncorrectable Error Logged Interrupt Mask - When ‘1’ the interrupt is masked
07 0 Received Configuration Retry Status (CRS) Mask - When ‘1’ the interrupt is masked
06 0 Link Down Interrupt Mask - When ‘1’ the interrupt is masked.
05 0 Internal Bus Master Abort Interrupt Mask - When ‘1’ the interrupt is masked
04 0 Data Parity Error Interrupt Mask - When ‘1’ the interrupt is masked
03 0 Received Master Abort Interrupt Mask - When ‘1’ the interrupt is masked
02 0 Signaled Target Abort Interrupt Mask - When ‘1’ the interrupt is masked
01 0 Received Target Abort Interrupt Mask - When ‘1’ the interrupt is masked
00 0 Master Data Parity Error Interrupt Mask - When ‘1’ the interrupt is masked
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
rv
rv
rv
rv
rv
rw
rw
rv
rv
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rw
rw
rw
rw
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+07CH