Intel CONTROLLERS 413808 - Manual (Page 17)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 17
Contents—Intel
®
413808 and 413812
12.4.6 SMBus Controller ADDR0 Register Number — SM_ADDR0 .......................... 657
12.4.7 SMBus Controller Data Register — SM_DATA............................................ 658
12.4.8 SMBus Controller Status Register — SM_STS ........................................... 658
13.0 UARTs..................................................................................................................... 659
13.1 Overview ....................................................................................................... 659
13.1.1 Compatibility with 16550 and 16750....................................................... 660
13.2 Signal Descriptions.......................................................................................... 661
13.3 Theory of Operation......................................................................................... 662
13.3.1 FIFO Interrupt Mode Operation............................................................... 663
13.3.1.1 Receiver Interrupt................................................................... 663
13.3.1.2 Transmit Interrupt .................................................................. 663
13.3.2 Removing Trailing Bytes In Interrupt Mode .............................................. 664
13.3.2.1 Character Time-out Interrupt ................................................... 664
13.3.3 FIFO Polled Mode Operation................................................................... 664
13.3.3.1 Receive Data Service............................................................... 664
13.3.3.2 Transmit Data Service ............................................................. 664
13.3.4 Autoflow Control .................................................................................. 665
13.3.4.1 RTS Autoflow ......................................................................... 665
13.3.4.2 CTS Autoflow ......................................................................... 665
13.3.5 Auto-Baud-Rate Detection ..................................................................... 666
13.3.6 Manual Baud Rate Selection................................................................... 667
13.4 Register Descriptions ....................................................................................... 668
13.4.1 UART x Receive Buffer Register.............................................................. 670
13.4.2 UART x Transmit Holding Register .......................................................... 670
13.4.3 UART x Interrupt Enable Register ........................................................... 671
13.4.4 UART x Interrupt Identification Register .................................................. 672
13.4.5 UART x FIFO Control Register................................................................. 674
13.4.6 UART x Line Control Register ................................................................. 676
13.4.7 UART x Modem Control Register............................................................. 678
13.4.8 UART x Line Status Register .................................................................. 680
13.4.9 UART x Scratchpad Register .................................................................. 684
13.4.10Divisor Latch Registers.......................................................................... 685
13.4.11UART x FIFO Occupancy Register............................................................ 686
13.4.12UART x Auto-Baud Control Register ........................................................ 687
13.4.13UART x Auto-Baud Count Register .......................................................... 688
14.0 I
2
C Bus Interface Units.............................................................................................. 689
14.1 Overview ....................................................................................................... 689
14.2 Theory of Operation......................................................................................... 690
14.2.1 Operational Blocks................................................................................ 692
14.2.2 I
2
C Bus Interface Modes........................................................................ 694
14.2.3 Start and Stop Bus States ..................................................................... 695
14.2.3.1 START Condition..................................................................... 696
14.2.3.2 No START or STOP Condition .................................................... 696
14.2.3.3 STOP Condition ...................................................................... 696
14.3 I
2
C Bus Operation ........................................................................................... 697
14.3.1 Data and Addressing Management.......................................................... 697
14.3.1.1 Addressing a Slave Device ....................................................... 698
14.3.2 I
2
C Acknowledge.................................................................................. 699
14.3.3 Arbitration........................................................................................... 700
14.3.3.1 SCL Arbitration....................................................................... 700
14.3.3.2 SDA Arbitration...................................................................... 701
14.3.4 Master Operations ................................................................................ 702
14.3.5 Slave Operations.................................................................................. 705
14.3.6 General Call Address............................................................................. 707