Intel CONTROLLERS 413808 - Manual (Page 49)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 49
Introduction—Intel
®
413808 and 413812
1.6.3 Specifying Bit and Signal Values
The terms set and clear in this specification refer to bit values in register and data
structures. When a bit is set, its value is 1; when the bit is clear, its value is 0. Likewise,
setting a bit means giving it a value of 1 and clearing a bit means giving it a value of 0.
The terms assert and deassert refer to the logically active or inactive value of a signal
or bit, respectively.
1.6.4 Signal Name Conventions
All signal names use the PCI signal name convention of using the “#” symbol at the end
of a signal name to indicate that the signal’s active state occurs when it is at a low
voltage. The absence of the “#” symbol indicates that the signal’s active state occurs
when it is at a high voltage.
1.6.5 Terminology
To aid the discussion of the 81348 architecture, the following terminology is used:
Downstream At or toward a PCI bus with a higher number (after
configuration)
DWORD 32-bit data word
QWORD 64-bit data word
word 32-bit data word
Host processor Processor located upstream from the 81348
Local processor Intel XScale
®
processor within the 81348
Local bus 81348 Internal Bus
Local memory Memory subsystem on the Intel XScale
®
processor DDR SDRAM
or Peripheral Bus Interface busses
Upstream At or toward a PCI bus with a lower number (after configuration)