Intel CONTROLLERS 413808 - Manual (Page 398)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
398 Order Number: 317805-001US
4.0 Messaging Unit
This chapter describes the Messaging Unit (MU) of the Intel
®
413808 and 413812 I/O
Controllers (4138xx).
4.1 Overview
The Messaging Unit (MU) provides a mechanism for data to be transferred between the
PCI bus and the Intel XScale
®
processor and notifying the respective system of the
arrival of new data through an interrupt. The MU can be used to send and receive
messages.
The MU is located on the south internal bus of the 4138xx. External PCI agents access
the MU via the ATU. For example, the ATU initiates transactions on the internal bus to
the MU on behalf of the external PCI agents.
The MU has two distinct messaging mechanisms. Each allows a host processor or
external PCI agent and the 4138xx to communicate through message passing and
interrupt generation. The two mechanisms are:
• Message Registers — allow the 4138xx and external PCI agents to communicate
by passing messages in one of four 32-bit Message Registers. In this context, a
message is any 32-bit data value. Message registers combine aspects of mailbox
registers and doorbell registers. Writes to the message registers may optionally
cause interrupts.
• Doorbell Registers — allow the 4138xx to assert the PCI interrupt signals and
allow external PCI agents to generate an interrupt to the Intel XScale
®
processor.
Each of the above are available to the system designer at the same time. No special
mode selection is needed.