Intel CONTROLLERS 413808 - Manual (Page 192)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
192 Order Number: 317805-001US
6:4 011
2
Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions
the device is permitted to have outstanding at one time.
Register Maximum Outstanding
0 1
1 2
2 3
3 4
4 8
5 12
6 16
7 32
3:2 00
2
Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when
initiating a Sequence with one of the burst memory read commands.
Register Maximum Byte Count
0 512
1 1024
2 2048
3 4096
1 1
2
Enable Relaxed Ordering - When set, the 4138xx may set the relaxed ordering bit in the Requester
Attributes of Transactions.
0 0
2
Uncorrectable Data Error Recovery Enable - The device driver sets this bit to enable the device to
attempt to recover from uncorrectable data errors. When this bit is 0 and the device is in PCI-X mode,
the device asserts P_SERR# (when enabled) whenever the Master Data Parity Error bit (Status register,
bit 8) is set.
Table 82. PCI-X Command Register - PCIXCMD (Sheet 2 of 2)
Bit Default Description
PCI
IOP
Attributes
Attributes
15 12 8 4 0
rv
rv
rv
rv
ro
ro
ro
ro
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+0D2H