Address translation unit (pci-x)—intel, Bit default description – Intel CONTROLLERS 413808 User Manual
Page 223
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
223
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.85 PCI Interface Error Context Address Register — PCIECAR
When PCIECSR bit 0 is set, this register contains the DMA Channel Number and bits 30
through 5 of the address of the ADMA descriptor associated with the error detected on
the PCI Bus.One error can be detected and logged. The software knows which ADMA
descriptor context had the error by reading this register and decoding the contents of
the PCIECSR. For error details, see
Section 2.7, “ATU Error Conditions” on page 94
).
Table 112. PCI Interface Error Context Address Register - PCIECAR
Bit
Default
Description
31
0
Reserved
30:29
00
DMA Channel Number
28:0
0H
ADMA Descriptor Address Bits 30:5
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
rv
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register
Offset
+38CH