Intel CONTROLLERS 413808 - Manual (Page 179)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 179
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
21 1
Central Resource PCI Bus Reset - When set, P_RSTOUT# is asserted. When cleared, P_RSTOUT# is
deasserted. After clearing this bit, there is a delay of about 300 uS before hardware de-asserts the
P_RSTOUT# signal. After this bit is cleared, the hardware waits about 150 uS to allow the PLL to
warm-up and another 150 uS to allow the clocks to stabilize. Therefore, firmware has to wait about
300uS for the P_RSTOUT# signal to get de-asserted. After hardware de-asserts P_RSTOUT#, firmware
has to wait before issuing the first configuration cycle in order to meet the PCI timing parameter Trhfa
(about 2 26 PCI clocks). Note that the PCI timing parameter Trhfa is dependent on the PCI bus speed
selected.
Note: P_RSTOUT# is asserted by default. This output should remain unconnected when operating
as an endpoint.
20 0
2
Detected Uncorrectable Address or Attribute Error - set when an uncorrectable error is detected during
either the address or attribute phase of a transaction on the PCI bus even when the ATUCMD register’s
Parity Error Response bit is cleared. Set under the following conditions:
• Any Uncorrectable Address or Attribute (PCI-X Only) Error on the Bus (including one generated by
the ATU).
19:16
See
description
for default
value
PCI-X capability - These bits define the mode of the PCI bus (conventional or PCI-X) as well as the
operating frequency in the case of PCI-X mode and are consistent with the electrical value on the PCI
bus.
As a Central Resource, this field controls the initialization pattern driven on the PCI bus during reset and
the value driven on the CR_FREQ[1:0] pins. The default value of this field is dependent on
the
following pins/straps:
PCIXM1_100#
,
PCIXM2_100#
,
P_MODE2
,
P_PCIXCAP
, and
P_M66EN
.
As an endpoint, this register reflects the value captured off the bus during reset based on the following
signals: P_PERR#, P_DEVSEL#, P_STOP#, and P_TRDY#.
1111 - Conventional PCI mode(frequency depends on P_M66EN )
1110 - PCI-X 66
1101 - PCI-X 100
1100 - PCI-X 133
0110 - PCI-X 266 (66 MHz P_CLK )
0101 - PCI-X 266 (100 MHz P_CLK )
0100 - PCI-X 266 (133 MHz P_CLK )
All other values are reserved.
All other patterns are reserved or not supported by the 4138xx.
See Section 2.12.6, “Bus Mode and Frequency Initialization” on page 134 for more details.
15 0
2
Outbound Transaction Queue Busy:
0 = Outbound Transaction Queue Empty
1 = Outbound Transaction Queue Busy
14 0
2
Inbound Transaction Queue Busy:
0 = Inbound Transaction Queue Empty
1 = Inbound Transaction Queue Busy
13 0
2
Reserved
12 0
2
Discard Timer Value - This bit controls the time-out value for the four discard timers attached to the
queues holding read data. A value of 0 indicates the time-out value is 2 15 clocks. A value of 1 indicates
the time-out value is 2 10 clocks.
11 0
2
Reserved
Table 68. PCI Configuration and Status Register - PCSR (Sheet 2 of 3)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rw
rw
rc
rc
rw
rw
rw
rw
rw
rw
rw
rw
ro
ro
ro
ro
rv
rv
rw
rw
rv
rv
ro
ro
ro
ro
ro
ro
rc
rc
rv
rv
rv
rv
rv
rv
rv
rv
rw
ro
co
co
co
co
Attribute Legend:
RV = Reserved
CO = Clear Only
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+074H