Intel CONTROLLERS 413808 - Manual (Page 516)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
516 Order Number: 317805-001US
8.3.1.6 North Internal Bus Port Transaction Ordering
Since requests from the north internal bus port are queued in the NIBPTQ, the port
needs to maintain order of requests addressing the SRAM. Coherency between the
north internal bus port and the other ports are maintained by the SMCU as described in
“SMCU Port Coherency” below.
8.3.1.7 SMCU Port Coherency
With the queueing of SRAM transactions in multiple ports, coherency of memory must
be maintained. The SMARB maintains memory coherency by ensuring that all writes to
a given memory address are completed before any read to the same address is
processed. This address comparison is done with a 1 KByte granularity.
The current read transaction is compared to all pending write transactions in the
NIBPTQ transaction queue. If a write transaction is pending for the same memory
location (1 KByte granularity), the write is allowed to complete first, before the read
transaction can be processed. Also, to maintain ordering rules, all write transactions
preceding the ‘incoherent write’ are also processed.