Intel CONTROLLERS 413808 - Manual (Page 330)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
330 Order Number: 317805-001US
17 0
VPD Address Register Updated - Set when a configuration write occurs to the VPDAR register.
When set, this bit results in the assertion of the ATU Config Reg Write Interrupt.
16 0
Power State Transition - Set when the Power State Field of the ATU Power Management Control/Status
Register is written to transition from D0 ->D3, D0 ->D1, D1 -> D3, or D3 ->D0.
When set, this bit results in the assertion of the ATU Config Req Write Interrupt.
15:14 0 Reserved Zero - Software must write 0 to these bits
13 0
Halt on Error Interrupt - Set when an outbound address or data parity error is detected on a posted
write and the Halt on Error control (bit 8) is set in the “ATU Configuration Register - ATUCR”
12 0
Root System Error Interrupt - This bit set when the System Error enable bits are set in the “PCI Express
Root Control Register - PE_RCR” on page 353 and a non-masked ERR_FATAL, ERR_NONFATAL, or
ERR_COR message is received.
Note: A PCI Express Error message may also cause bit 11 to be set.
Generates the ATU Error Interrupt
11 0
Root Error Message received - Indicates a Root Complex error message was received and logged in the
“Root Error Status Register - RERR_SR”
Note: This read only bit is set when any of bits 6, 5, or 0 is set in the RERR_SR registers. To clear this
interrupt, these bit must be cleared in the RERR_SR register. The mask for this interrupt is
controlled by the “Root Error Command Register - RERR_CMD” register.
Generates the ATU Error Interrupt
10 0
PCI Interface Error - Indicates a non-masked error was logged in the “PCI Interface Error Status -
PIE_STS” register.
Note: This read only bit is an OR of the unmasked PIE_STS bits.
Generates the ATU Error Interrupt
09 0
Correctable Error Message Transmitted - Indicates a ERR_COR message was sent to the Root Complex.
A message is transmitted when a correctable error was logged and the corresponding mask is cleared in
the “PCI Express Correctable Error Mask - ERRCOR_MSK” register
Generates the ATU Error Interrupt
08 0
Uncorrectable Error Message Transmitted - Indicates an ERR_FATAL or ERR_NONFATAL message was
sent to the root complex. A message is transmitted when an uncorrectable error was logged and the
corresponding mask is cleared in the “PCI Express Uncorrectable Error Mask - ERRUNC_MSK” register
Generates the ATU Error Interrupt
07 0
Received Configuration Retry Status (CRS) - This bit set whenever an outbound configuration request is
completed with a CRS status.
Generates the ATU Error Interrupt
06 0 Link Down Interrupt - This bit is set whenever the PCI Express link goes down.
05 0
Internal Bus Master Abort - Set when a transaction initiated by the ATU internal bus initiator interface
ends in a Master-abort.
Note: An internal bus master abort may also result in the setting of the Signaled Target Abort.
Generates the ATU Error Interrupt
04 0
Detected Parity Error Interrupt - Set when a poisoned TLP is received by any function, regardless of the
state of the Parity Error Response.
Generates the ATU Error Interrupt
Table 182. ATU Interrupt Status Register - ATUISR (Sheet 2 of 3)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rz
rz
rz
rz
rz
rz
rc
rc
ro
ro
rc
rc
rc
rc
ro
ro
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rc
rc
rc
rc
rc
rc
rz
rz
rz
rz
rc
rc
rc
rc
ro
ro
ro
ro
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
Attribute Legend:
RZ = Reserved Zero
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+078H