Intel CONTROLLERS 413808 - Manual (Page 118)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
118 Order Number: 317805-001US
2.7.9.3 Parity Error on the Internal Bus
The 4138xx provides support for byte-wise parity protection on the internal bus. The
internal bus consists of a 36 bit address bus and 128 bit data bus; both are protected
by byte-wise parity. The internal bus parity protection is provided independent of the
operating mode of the ATUs PCI interface.
When initiating transactions on the internal bus, the ATUs internal bus interface
generates byte-wise parity. As a target the ATU checks byte-wise parity.
As an initiator, for outbound write transactions the ATU will forward bad data parity on
the PCI bus if the ATU detected a parity error on the internal bus interface. And for
outbound read transactions the ATU will forward bad data parity on the internal bus if
the ATU detected a parity error on the PCI interface. Outbound read parity error will be
detected and logged by the internal bus initiator. For outbound read data that has to
flow through the internal bus bridge, the bridge will log the error. Refer to the internal
bus bridge chapter for more details on how the parity error is handled.
As a target, for inbound read transactions the ATU will forward bad data parity on the
PCI bus if the ATU detected a parity error on the internal bus interface. And for inbound
write transactions the ATU will forward bad data parity on the internal bus if the ATU
detected a parity error on the PCI interface. Inbound write parity error will be detected
and logged by the internal bus target. For write data that has to flow through the
internal bus bridge, the bridge will log the error. Refer to the internal bus bridge
chapter for more details on how the parity error is handled.
2.7.9.3.1 Conventional Mode
On an inbound read transaction, when the data word where the internal bus parity
error is detected is actually requested and returned to the PCI bus, a target abort is
returned to the PCI initiator on that data word. The IRQ is flushed after the completion
cycle is performed on the PCI bus
The following additional actions with the given constraints are performed by the ATU
when a target abort is signaled by the PCI target interface during an inbound read
transaction:
• Set the Target Abort (target) bit (bit 11) in the ATUSR.
• When the ATU PCI Target Abort (target) Interrupt Mask bit in the ATUIMR is clear,
set the PCI Target Abort (target) bit in the ATUISR. When set, no action.
2.7.9.3.2 PCI-X Mode
An internal bus parity error of an inbound read transaction (split read request) on the
Internal Bus results in the following actions.
• The ATU initiates a Split Completion Error Message (with message class=2h -
completer error and message index=81h - 4138xx internal bus target abort) on the
PCI bus.
• When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is
clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set,
no action.
Note: This split completion error message includes a device specific message index. The error
handler would need to have knowledge of the device specific error messages of the
4138xx in order to fully diagnose the problem.