Intel CONTROLLERS 413808 - Manual (Page 515)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 515
SRAM Memory Controller—Intel
®
413808 and 413812
8.3.1.5.2 Error Correction Logic
The Error Correction Logic generates the ECC code for SRAM reads and writes. For
reads, this logic compares the ECC codes read with the locally generated ECC code. If
the codes mismatch then the Error Correction Logic determines the error type. For a
single-bit error, this block determines which bit is in error and corrects the error. For a
single-bit or multi-bit error, the Error Correction Logic logs the error in ELOG0 and
ELOG1. See Section 8.3.3, “Error Correction and Detection” on page 519 for more
details.