Intel CONTROLLERS 413808 - Manual (Page 532)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
532 Order Number: 317805-001US
8.4.1 Single-Bit Error Detection
When enabled, the SMCU interrupts the core when the ECC logic detects a single-bit
error by setting the appropriate bit in the MCISR register. The core knows the interrupt
was caused by a single-bit error by polling the SELOG register. The SRAM Control Block
ensures that correct data is returned but the interrupt handler is responsible for
scrubbing the error in the array (refer to Section 8.3.3.4, “Scrubbing” on page 526 ).
An example flow for a single-bit error with error detection and reporting enabled is:
• A single-bit ECC error is detected on the data bus by the SMCU.
• SMCU fixes the error prior to returning the data.
• SMCU clears SELOG[8] indicating a single-bit error.
• SMCU records requester of transaction that resulted in an error in SELOG[23:16]
• The SMCU loads SELOG[7:0] with the syndrome that indicated the error.
• The SMCU loads SECAR[31:2] and SECUAR with address where the error occurred.
• Since the core needs to scrub the error in the array, the SMCU sets MCISR[0] to 1
(assuming it is not already set).
— Setting any bit in the MCISR causes an interrupt to the core.
• Software polls interrupt status register. Bit 0 = 1 indicates first error has occurred.
• Software polls SELOG, SECAR and SECUAR and scrubs the error at the location
specified by SECAR and SECUAR.
• Software writes a 1 to SMCISR[0] thereby clearing it.
If software does not perform error scrubbing, the probability of an unrecoverable
multi-bit error increases for the memory location containing the single-bit error.
SECAR, SECUAR and SELOG remain registered until software explicitly clears them.
If a second error occurs before software clears the first by resetting SMCISR[0], the
error is not logged but the SMCU carries out the action described in Table 348 .