Intel CONTROLLERS 413808 - Manual (Page 755)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 755
PMON Unit—Intel ® 413808 and 413812
25 0b
Command Trigger Indicator (CTI)
0 = NO commands have been triggered since the last time this bit was cleared.
1 = A command WAS triggered since the last time this bit was cleared.
Software can use this bit to know that a command that was pending earlier has been triggered. Once a
command has been triggered, another command can be triggered to execute.
The null event does not cause this Command Trigger Indicator to be asserted.
24 0b
Threshold Indicator (THI)
0 = No threshold event has been generated since the last time this bit was cleared.
1 = This counter generated a threshold event due to a true threshold condition compare since the last
time this bit was cleared.
23:12 000h Reserved
11:4 TBD
Clock Period (CP)
This fixed point field is 5.3 format which allows representing clock periods from 0.125 ns (8 GHz) to
31.875 ns (a little over 31 MHz) in 125 ps increments.
Example: 100 MHz = 10.000 ns period = 01010.000b = 50h
Example: 133 MHz = 7.500 ns period = 00111.100b = 3Ch
Example: 167 MHz = 6.000 ns period = 00110.000b = 30h
Example: 200 MHz = 5.000 ns period = 00101.000b = 28h
3:0 0h Reserved
Table 494. PMON Status Register 0-7 - PMON_STS[0:7] (Sheet 2 of 2)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rc
rc
rc
rc
ro
ro
sc
sc
rc
rc
rc
rc
rc
rc
rc
rc
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rv
rv
rv
rv
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
SC = Read Set/Write Clear
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
PMON _STS0
PMON _STS1
PMON _STS2
PMON _STS3
PMON _STS4
PMON _STS5
PMON _STS6
PMON _STS7
+008h
+018h
+028h
+038h
+048h
+058h
+068h
+078h