Intel CONTROLLERS 413808 - Manual (Page 821)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 821
Peripheral Registers—Intel ® 413808 and 413812
Interrupt Steering Register 0
5
Register 0
Interrupt Steering Register 1 Register 1
Interrupt Steering Register 2 Register 2
Interrupt Steering Register 3 Register 3
Undefined Register 4–15
In
ter
ru
pt
Co
ntr
ol
Un
it
IRQ Interrupt Source Register 0 CP6
6
Register 0
IRQ Interrupt Source Register 1 Register 1
IRQ Interrupt Source Register 2 Register 2
IRQ Interrupt Source Register 3 Register 3
Undefined Register 4–15
FIQ Interrupt Source Register 0
7
Register 0
FIQ Interrupt Source Register 1 Register 1
FIQ Interrupt Source Register 2 Register 2
FIQ Interrupt Source Register 3 Register 3
Undefined Register 4–15
Interrupt Priority Register 0
8
Register 0
Interrupt Priority Register 1 Register 1
Interrupt Priority Register 2 Register 2
Interrupt Priority Register 3 Register 3
Interrupt Priority Register 4 Register 4
Interrupt Priority Register 5 Register 5
Interrupt Priority Register 6 Register 6
Interrupt Priority Register 7 Register 7
Undefined Register 8–15
Table 549. Coprocessor Register Locations (Sheet 2 of 4)
Peripheral Register Description (Name) Coprocessor Field CR
m
Coprocessor
Register
(Field CR
n
)