Intel CONTROLLERS 413808 - Manual (Page 409)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 409
Messaging Unit—Intel
®
413808 and 413812
Figure 42 shows how the MSI-X Table and Pending Bits Array are mapped from the host
I/O interface. The MU registers are located in the first 4-KByte of the 8-KByte address
space.
4.6.3 Level-Triggered Versus Edge-Triggered Interrupts
When MSI and MSI-X are disabled, the P_INTA# pin remains asserted and pended to
the host when any of the MU interrupt sources requires service (Outbound Post Queue,
Outbound Doorbell and Outbound Message). Since the PCI pin signaled interrupt is
level-triggered , the interrupt service routine does not drop out of the service routine
until the interrupt signal is deasserted. This insures that an interrupt is not missed.
MSI interrupts are inherently edge-triggered, in that an interrupt is only pended to the
host as a write event when any of the MU interrupt sources requires service.
Note: Bit[10] (Interrupt Disable bit) of the ATUs ATU Command Register (ATUCMD) must be
cleared for the P_INTA# interrupt to be generated to the Host processor. Bit[3]
(Interrupt Status bit) of the ATU’s ATU Status Register (ATUSR) is not affected by the
state of bit[10] of the ATUCMD.
Figure 42. MSI-X Table and PBA Address Mapping Layout relative to the Internal Bus
MU Registers
Offset Relative to PMMRBAR
MSI-X PBA
MSI-X Table
+ 4000H
+ 5000H
+ 5800H
8 KBytes
4 KB
4 KB
2 KB
2 KB
B6217-01