Intel CONTROLLERS 413808 - Manual (Page 415)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 415
Messaging Unit—Intel
®
413808 and 413812
4.7.5 Inbound Interrupt Mask Register - IIMR
The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale
®
processor interrupts generated by the Messaging Unit. Each bit in the Mask register
corresponds to an interrupt bit in the Inbound Interrupt Status Register.
Setting or clearing bits in this register does not affect the Inbound Interrupt Status
Register. They only affect the generation of the Intel XScale
®
processor interrupt.
Table 270. Inbound Interrupt Mask Register - IIMR
Bit Default Description
31 0
2
Coordinated Reset Interrupt Mask - When set, this bit masks the interrupt generated by the Coordinated
Reset bit (bit 1) in the Inbound Reset Control and Status Register is set.
30 0
2
Selective Reset Interrupt Mask - When set, this bit masks the interrupt generated by the Selective Reset
bit (bit 0) in the Inbound Reset Control and Status Register is set.
29 0
2
MU MSI-X Table Write Interrupt Mask - Controls the setting of bit 29 of the “Inbound Interrupt Status
Register - IISR” and generation of the MU MSI-X Table Write Interrupt when a write occurs to any of the
MU MSI-X Table entry.
0 = Not Masked
1 = Masked
28:07 000000H Reserved
06 0
2
Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware
when an Index Register has been written after a Host I/O Interface transaction.
05 0
2
Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated when
the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
04 0
2
Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated by the MU
hardware when the Inbound Post Queue has been written.
03 0
2
Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt when the Error Interrupt bit
of the Inbound Doorbell Register is set.
02 0
2
Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated when at least one
Normal Interrupt bit in the Inbound Doorbell Register is set.
01 0
2
Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 Interrupt
generated by a write to the Inbound Message 1 Register.
00 0
2
Inbound Message 0 Interrupt Mask - When set, this bit masks the Inbound Message 0 Interrupt
generated by a write to the Inbound Message 0 Register.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
MU/PCI Base Address Offset
IIMR: 0028H
internal bus address offset
IIMR: 4028H