Address translation unit (pci express)—intel, Bit default description, Intel – Intel CONTROLLERS 413808 User Manual

Page 385

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Intel

®

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

385

Address Translation Unit (PCI Express)—Intel

®

413808 and 413812

3.17.106 Inbound Vendor Message Header Register 1 - IVMHR1

The Inbound Vendor Message Header Registers capture the header for a vendor defined

message received on the PCI Express interface. Once the inbound message has been

processed, the Inbound Vendor Message Received bit is set in the

ATU Interrupt Status

Register - ATUISR

. Subsequent inbound vendor messages are held in the inbound

posted queues until the status bit is cleared or the mask bit is set in the

ATU Interrupt

Mask Register - ATUIMR

. When the mask bit is set, then Vendor_Defined Type 0

messages are treated as unsupported requests and Vendor_Defined Type 1 messages

are silently discarded.

Table 246. Inbound Vendor Defined Message Header Register 1 - IVMHR1

Bit

Default

Description

31:24

00H

Header Byte 4

23:16

00H

Header Byte 5

15:8

00H

Header Byte 6

7:0

00H

Header Byte 7

PCI

IOP

Attributes

Attributes

28

24

20

16

12

8

4

0

31

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+344H

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