Intel CONTROLLERS 413808 - Manual (Page 636)

Intel ® 413808 and 413812—Timers
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
636 Order Number: 317805-001US
11.4.2.4 Bit 3 — Timer Register Privileged Read/Write Control (TMRx.pri)
The TMRx.pri bit enables or disables user mode writes to the timer registers (TMRx,
TCRx, TRRx). Privileged mode writes are allowed regardless of this bit’s condition.
Software can read these registers from either mode. Note that TMR1.pri also controls
write access to the “Watch Dog Timer Control Register — WDTCR” on page 639 and the
“Watch Dog Timer Setup Register — WDTSR” on page 639 .
When:
The processor clears TMRx.pri upon hardware or software reset.
11.4.2.5 Bits 4, 5 — Timer Input Clock Select (TMRx.csel1:0)
User software programs the TMRx.csel bits to select the Timer Clock (TCLOCK)
frequency. See Table 421 . As shown in Figure 71 , the internal bus clock is an input to
the timer clock unit. These bits allow the application to specify whether TCLOCK runs at
or slower than the internal bus clock frequency.
The processor clears these bits upon hardware or software reset
(TCLOCK = Core Clock).
TMRx.pri = 1 The timer ignores the user mode write to the timer registers;
however, writes from the privileged modes are allowed.
TMRx.pri = 0 The timer registers can be written from either the user mode or
the privileged modes.
Table 421. Timer Input Clock (TCLOCK) Frequency Selection
Bit 5
TMRx.csel1
Bit 4
TMRx.csel0
Timer Clock (TCLOCK)
0 0 Timer Clock = internal bus clock
0 1 Timer Clock = internal bus clock / 4
1 0 Timer Clock = internal bus clock / 8
1 1 Timer Clock = internal bus clock / 16