Intel CONTROLLERS 413808 - Manual (Page 124)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
124 Order Number: 317805-001US
Table 19. ATU Error Reporting Summary - Internal Bus Interface
Error
Condition
a
(Bus Mode
b
)
Bits Set in
ATU Status Register
(ATUSR
c
)
Bits Set in
ATU Interrupt Status
Register (ATUISR)
Interrupt Mask Bit in
ATUIMR or ATUCR
PCI Bus Error Response (i.e., signal Target-Abort, signal Master-Abort etc.)
Inbound Write
Request
Master-Abort
(All)
Assert SERR# .
(All) N/A
Internal Bus Master Abort - bit
7
N/A
(All) SERR# Asserted - bit 14 SERR# Asserted - bit 10 ATUIMR bit 6
(All) N/A SERR# Detected - bit 4 ATUCR bit 9
Inbound Read
Request
Master-Abort
(All)
In the Conventional Mode signal Target-Abort. In the PCI-X Mode send a device specific
Split Completion Error Message to the Requester.
(All) N/A
Internal Bus Master Abort - bit
7
N/A
(Conventional) Target Abort (target) - bit 11 PCI Target Abort (target) - bit 1 ATUIMR bit 3
(PCI-X) N/A
Initiated Split Completion Error
Message - bit 13
ATUIMR bit 10
Inbound Read
Request
Target-Abort
(All)
In the Conventional Mode signal Target-Abort. In the PCI-X Mode send a device specific
Split Completion Error Message to the Requester.
(Conventional) Target Abort (target) - bit 11 PCI Target Abort (target) - bit 1 ATUIMR bit 3
(PCI-X) N/A
Initiated Split Completion Error
Message - bit 13
ATUIMR bit 10
a. There are no Inbound Write Request Target-Abort Error Conditions.
b. Codes for bus mode in which this error response applies: PCI-X means PCI-X Mode 1 or PCI-X Mode 2, PCI-X2
means PCI-X Mode 2 only, Conventional means Conventional PCI Mode Only, and All means that the error
response applies in the Conventional, PCI-X Mode 1 and PCI-X Mode 2 modes of operation. MSI stands for
Message-Signaled Interrupts and refers to an Outbound Write transaction that is actually an MSI write
transaction.
c. Table assumes that the ATU Inbound SERR# Enable bit (bit 1 of the ATUIMR), the ATU ECC Target Abort
Enable (bit 0 of the ATUIMR), and the SERR# Enable bit (bit 8 of the ATUCMD) are set.