Intel CONTROLLERS 413808 - Manual (Page 422)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
422 Order Number: 317805-001US
4.7.12 MU Configuration Register - MUCR
The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the
size of one Circular Queue. The Circular Queue Enable bit enables or disables the
Circular Queues. The Circular Queues are disabled at reset to allow the software to
initialize the head and tail pointer registers before any PCI accesses to the Queue Ports.
Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256
Kbytes) and there are four Circular Queues.
This register also contains the upper four bits of the 36-bit QBR address. Local memory
is 36-bit addressable.
Table 277. MU Configuration Register - MUCR
Bit Default Description
31:20 000H Reserved
19:16 0H Reserved
15:06 000000H Reserved
05:01 00001
2
Reserved
00 0
2
Must be 0 for 4138xx.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
MUCR
internal bus address offset
4050H