60 pci express device status register - pe_dsts, 60pci express device status register - pe_dsts, 200 pci express device status register pe_dsts – Intel CONTROLLERS 413808 User Manual
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Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
346
Order Number: 317805-001US
3.17.60 PCI Express Device Status Register - PE_DSTS
This register controls various modes and features of ATU and Message Unit when
operating in the PCI Express mode.
Table 200. PCI Express Device Status Register PE_DSTS
Bit
Default
Description
15:6
00
2
Reserved Zero - Software must write 0 to these bits.
5
0
Transactions Pending – This bit when set indicates that a device has issued Non-Posted Requests which
have not been completed. A device reports this bit cleared only when all Completions for any
outstanding Non-Posted Requests have been received.
4
0
AUX Power Detected – ATU does not utilize AUX power. Hard-wired to 0.
3
0
Unsupported Request Detected – This bit indicates that the device received an Unsupported Request.
Errors are logged in this register regardless of whether error reporting is enabled or not in the Device
Control Register.
For a multi-function device, each function indicates status of errors as perceived by the respective
function.
2
0
Fatal Error Detected – This bit indicates status of fatal errors detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control register. For devices
supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the
correctable error mask register.
For a multi-function device, each function indicates status of errors as perceived by the respective
function.
1
0
Non-Fatal Error Detected – This bit indicates status of non-fatal errors detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device Control register. For
devices supporting Advanced Error Handling, errors are logged in this register regardless of the settings
of the correctable error mask register.
For a multi-function device, each function indicates status of errors as perceived by the respective
function.
0
0
Correctable Error Detected – This bit indicates status of correctable errors detected. Errors are logged in
this register regardless of whether error reporting is enabled or not in the Device Control register. For
devices supporting Advanced Error Handling, errors are logged in this register regardless of the settings
of the correctable error mask register.
For a multi-function device, each function indicates status of errors as perceived by the respective
function.
PCI
IOP
Attributes
Attributes
15
12
8
4
0
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
ro
ro
ro
ro
rc
rc
rc
rc
rc
rc
rc
rc
Attribute Legend:
RZ = Reserved Zero
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+0DAH