Intel CONTROLLERS 413808 - Manual (Page 369)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 369
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.90 Power Budgeting Capability Register - PWRBGT_CAP
Table 230. Power Budgeting Capability Register - PWRBGT_CAP
Bit Default Description
31:1 00_0000H Preserved
0 0
System Allocated – This bit when set indicates that the power budget for the device is included within
the system power budget. Reported Power Budgeting Data for this device should be ignored by software
for power budgeting decisions when this bit is set.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
ro
Attribute Legend:
RZ = Reserved Zero
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+1FCH