117 pci interface error mask - pie_msk, Table 257. pci interface error mask - pie_msk, 117pci interface error mask - pie_msk – Intel CONTROLLERS 413808 User Manual
Page 394: 257 pci interface error mask - pie_msk, Pci interface error mask - pie_msk, Intel, Bit default description
Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
394
Order Number: 317805-001US
3.17.117 PCI Interface Error Mask - PIE_MSK
The PCI Interface Error Mask register controls reporting of individual errors by the
device to the Intel XScale
®
processor core via an interrupt (ATUISR bit 10). A masked
error (respective bit set to 1b in the mask register) is not logged in the Header Log
register, does not update the First Error Pointer, and generate an interrupt to the core.
Table 257. PCI Interface Error Mask - PIE_MSK
Bit
Default
Description
31
0
Received Completion with Unsupported Request Mask
30
0
Received Completion with Completer Abort Mask
29
0
Poisoned TLP Transmitted Mask
28
0
Transmit: Header Parity Error Mask
27:21
0
Reserved Zero - Software must write 0 to these bits.
20
0
Unsupported Request Error Status Error Mask - When ‘1’ error reporting is masked.
19
0
ECRC Check Error Mask - When ‘1’ error reporting is masked.
18
0
Malformed TLP Error Mask - When ‘1’ error reporting is masked.
17
0
Receiver Overflow Error Mask - When ‘1’ error reporting is masked.
16
0
Unexpected Completion Error Mask - When ‘1’ error reporting is masked.
15
0
Completer Abort Error Mask - When ‘1’ error reporting is masked.
14
0
Completion Time Out Error Mask - When ‘1’ error reporting is masked.:
13
0
Flow Control Protocol Error Status Error Mask - When ‘1’ error reporting is masked.
12
0
Poisoned TLP Received Error Mask - When ‘1’ error reporting is masked.
11:5
0
Preserved.
4
0
Data Link Protocol Error Mask - When ‘1’ error reporting is masked.
3:1
0
Preserved.
0
0
Training Error Mask - When ‘1’ error reporting is masked.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
rw
pr
pr
pr
pr
pr
pr
rw
rw
Attribute Legend:
RZ = Reserved Zero
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+388H