Intel CONTROLLERS 413808 - Manual (Page 254)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
254 Order Number: 317805-001US
3.3.5.3 Outbound PCI Express Message Transactions
The ATU provides a port programming model to generate outbound PCI Express
messages.
Generating an outbound message transaction to the PCI Express interface involves up
to 5 internal bus cycles.
1. Write outbound message transaction header registers 0 - 3.
2. Write the data to the outbound message transaction payload register. This write
causes the generation of the message TLP on the PCI Express interface.
Note: When the payload length is 0, a write to the payload register is still required but the
written data is ignored and not sent as part of the message TLP.
3.3.5.4 Completion Timeout Mechanism
The ATU implements a completion timeout mechanism on all outbound requests that
require completions. The timeout mechanism is fixed and ensures an expiration time
between 16 and 32 ms.