Intel CONTROLLERS 413808 - Manual (Page 109)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 109
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.5 Master Aborts on the PCI Interface
As an initiator on the PCI bus, the ATU can encounter master abort conditions during:
• Outbound Read Request
• Outbound Write Request
• Inbound Read Completion
• Inbound Configuration Write Completion Message
As a target, the ATU PCI interface is capable of signaling a master abort case during:
• Uncorrectable Address Error (Conventional Mode)
• Inbound Read Request (PCI-X Mode)
2.7.5.1 Master Aborts for Outbound Read or Write Request
This error may be encountered in both the Conventional and the PCI-X modes. For an
Outbound transaction, there are two ways in which a Master-Abort may be signaled to
the ATU:
1. In the Conventional or PCI-X modes, a master abort is signaled when the target of
the transaction does not assert DEVSEL# within 5 clocks (7 clocks when operating
in the PCI-X mode) of the assertion of FRAME# .
2. In PCI-X mode, ATU may enqueue a Split request (Read or Write) on target-side
interface of a PCI-to-PCI Bridge. When PCI-to-PCI Bridge detects a Master Abort on
requester-side interface for that Split Request, master abort is signaled to ATU
through a Master-Abort Split Completion Error Message (class=1h - bridge error
and index=00h - Master Abort). The following actions with given constraints are
performed by ATU when a master abort is detected by the PCI initiator interface or
the PCI target interface receives a Master-Abort Split Completion error message:
• Set the Master Abort bit (bit 13) in the ATUSR.
• When the ATU PCI Master Abort Interrupt Mask bit in the ATUIMR is clear, set the
PCI Master Abort bit in the ATUISR. When set, no action.
• When an outbound write or inbound completion, flush data and address.
• When the transaction is an MSI outbound write and the SERR# Enable bit in the
ATUCMD is set, assert SERR# , otherwise no action. When the ATU asserts SERR#,
additional actions are taken:
— Set the SERR# Asserted bit in the ATUSR
— When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set
the SERR# Asserted bit in the ATUISR. When set, no action.
— When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set
the SERR# Detected bit in the ATUISR. When clear, no action
• When operating in PCI-X mode and Master-Abort is signaled via a Split Completion
Error Message, the Received Split Completion Error Message bit in PCIXSR is set.
When ATU sets this bit, additional actions are taken:
— When the ATU Received Split Completion Error Message Interrupt Mask bit in
the ATUIMR is clear, set the Received Split Completion Error Message bit in the
ATUISR. When set, no action.
• For an Outbound Read request, generate a split completion error message
(class=1h - 4138xx Outbound Request error and index=00h - master abort) on the
internal bus.
• Flush the address from the OTQ.