Intel CONTROLLERS 413808 User Manual
Page 818
Intel
®
413808 and 413812—Peripheral Registers
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
818
Order Number: 317805-001US
Inbound Vendor Defined Message Payload Register — IVMPR
32
+350H
Reserved.
x
+354H through +35FH
Outbound Vendor Defined Message Header Register0 — OVMHR0
32
+360H
Outbound Vendor Defined Message Header Register 1 — OVMHR1
32
+364H
Outbound Vendor Defined Message Header Register 2 — OVMHR2
32
+368H
Outbound Vendor Defined Message Header Register 3 — OVMHR3
32
+36CH
Outbound Vendor Defined Message Payload Register — OVMPR
32
+370H
Reserved.
x
+374H through +37FH
PCI Interface Error Control and Status Register — PIE_CSR
32
+380H
PCI Interface Error Status — PIE_STS
32
+384H
PCI Interface Error Mask — PIE_MSK
32
+388H
PCI Interface Error Header Log — PIE_LOG0
32
+38CH
PCI Interface Error Header Log 1 — PIE_LOG1
32
+390H
PCI Interface Error Header Log 2 — PIE_LOG2
32
+394H
PCI Interface Error Header Log — PIE_LOG3
32
+398H
PCI Interface Error Header Log — PIE_DLOG
32
+39CH
Reserved.
x
+3A0H through +FFFH
Table 546. Address Translation Unit Registers — ATUE (Sheet 4 of 4)
Register Description (Name)
Register
Size in
Bits
Internal Bus Address Offset
(Relative to ATUE Base
Address Offset)
Notes:
1.
MSI and MSI-X Capability Registers are documented in the Messaging Unit Chapter.