Intel CONTROLLERS 413808 - Manual (Page 735)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 735
PMON Unit—Intel ® 413808 and 413812
However, execution of this command is conditional upon a cache hit occurring (Event B
in Example 8 ). Thus, the cache hit command becomes the “Command Trigger” that
must occur before the memory read events would no longer be counted.
Example 8. How many Event A’s happen before the first Event B is detected
This example demonstrates how to measure the number of times event A occurs before
the first occurrence of event B.
Table 482. Hardware Event Based Event Counting Example
Opcode
Target
Counter
Increment
Event
Decrement
Event
Trigger Event
Write Event Register 0 Event A None (000h)
Start 0 Immed (000h)
Stop 0 Event B
Sample 0 Immed (000h)
Read Data Register 0
Figure 111. Block Diagram and Waveforms of Time Based Sampling Example
B6301-01