Intel CONTROLLERS 413808 - Manual (Page 50)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
50 Order Number: 317805-001US
2.0 Address Translation Unit (PCI-X)
This chapter describes the operation modes, setup, and implementation of the module
which interfaces between the PCI bus and the Intel
®
413808 and 413812 I/O
Controllers in TPER Mode (4138xx) internal bus.
2.1 Overview
As indicated in Figure 3 , the Address Translation Unit (ATU) — the interface between
the PCI bus and the on-chip internal bus — consists of the Address Translation Unit
(ATU) and the Expansion ROM Unit.
The ATU supports both inbound and outbound address translation. The ATU provides
access between the PCI bus and the 4138xx internal bus.
Transactions initiated on the PCI bus and targeted at the 4138xx internal bus are
referred to as inbound transactions (PCI to internal bus). Transactions initiated on the
4138xx internal bus and targeted at the PCI bus are referred to as outbound
transactions (internal bus to PCI). The ATU accepts multiple inbound or outbound
transactions and processes them simultaneously.
During inbound transactions, the ATU converts PCI addresses (initiated by a PCI bus
master) to Internal Bus Addresses and initiates the data transfer on the 4138xx
internal bus. During outbound transactions, the ATU converts internal bus addresses to
PCI addresses and initiates the data transfer on the PCI bus.
The Expansion ROM provides the PCI mechanism for downloading device/board driver
code during system boot sequence. It consists of a separate inbound address range
which accesses a Flash EPROM device connected through the 4138xx memory
controller. Refer to the PCI Local Bus Specification, Revision 2.3 for details of Expansion
ROM usage.
The Address Translation Unit and the Expansion ROM Translation Unit represent a single
function of the multi-function 4138xx PCI device.
The ATU supports the following PCI operating modes and bus widths delivering up to
2133 Mbytes/sec of bandwidth:
— Conventional Modes: PCI 33, PCI 66
— PCI-X Modes: Mode 1 (PCI-X 66, PCI-X 133), Mode 2 (PCI-X 266)
3
— Bus Widths: 64-bit, 32-bit
In Mode 2, all transaction phases are ECC protected (when enabled). In the remaining
PCI-X and Conventional modes supported by 4138xx, all transaction phases are parity
protected (when enabled).
On the internal interface, the ATU implements the 4138xx internal bus protocol which
provides for a maximum of 4800 Mbytes/sec of bandwidth.
3. PCIX is not supported in TPER mode.