Intel CONTROLLERS 413808 - Manual (Page 173)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 173
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.34 Inbound ATU Limit Register 2 - IALR2
Inbound address translation for inbound window 2 occurs for data transfers occurring
from the PCI bus (originated from the PCI bus) to the 4138xx internal bus. The address
translation block converts PCI addresses to internal bus addresses.
The inbound translation base address for inbound window 2 is specified in
Section 2.14.17 . When determining block size requirements — as described in
Section 2.14.23 — the translation limit register provides the block size requirements for
the base address register. The remaining registers used for performing address
translation are discussed in Section 2.2.1.1 .
The 4138xx value register’s programmed value must be naturally aligned with the base
address register’s programmed value. The limit register is used as a mask; thus, the
lower address bits programmed into the 4138xx value register are invalid. Refer to the
PCI Local Bus Specification, Revision 2.3 for additional information on programming
base address registers.
Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12,
with a one to one correspondence. A value of 0 in a bit within the IALR2 makes the
corresponding bit within the IABAR2 a read only bit which always returns 0. A value of
1 in a bit within the IALR2 makes the corresponding bit within the IABAR2 read/write
from PCI. Note that a consequence of this programming scheme is that unless a valid
value exists within the IALR2, all writes to the IABAR2 has no effect since a value of all
zeros within the IALR2 makes the IABAR2 a read only register.
Note: Bit 0 can be used to disable claiming of PCI Cycles that hit Inbound Window 1 even
though the host processor has allocated memory of the size requested by
IABAR2/IALR2[31:12].
. Table 61. Inbound ATU Limit Register 2 - IALR2
Bit Default Description
31:12 00000H
Inbound Translation Limit 2 - This value determines the memory block size required for the ATUs
memory window 2.
11:01 000H Reserved
00 0
2
Window 2 Claim Disable -- When this bit is set, Inbound Window 2 does not claim cycles on the PCI Bus.
When clear, Inbound Memory Window 2 claims PCI Cycles Normally.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+058H