Intel CONTROLLERS 413808 - Manual (Page 29)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 29
Contents—Intel
®
413808 and 413812
272 Outbound Interrupt Status Register - OISR................................................................ 417
273 Outbound Interrupt Mask Register - OIMR................................................................. 418
274 Inbound Reset Control and Status Register - IRCSR.................................................... 419
275 Outbound Reset Control and Status Register - ORCSR................................................. 420
276 MSI Inbound Message Register - MIMR ..................................................................... 421
277 MU Configuration Register - MUCR............................................................................ 422
278 MU Base Address Register - MUBAR.......................................................................... 423
279 MU Upper Base Address Register - MUUBAR .............................................................. 424
280 MU MSI-X Table Message Address Registers - M_MT_MAR [0:7] ................................... 425
281 MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]........................ 426
282 MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]........................ 427
283 MU MSI-X Table Message Vector Control Registers - M_MT_MVCR [0:7] ........................ 428
284 MU MSI-X Pending Bits Array Register - M_MPBAR...................................................... 429
285 MSI Capability Identifier Register - MSI_Cap_ID......................................................... 429
286 MSI Next Item Pointer Register - MSI_Next_Ptr ......................................................... 430
287 Message Control Register - Message_Control ............................................................. 431
288 Message Address Register - Message_Address ........................................................... 432
289 Message Upper Address Register - Message_Upper_Address ........................................ 433
290 Message Data Register - Message_Data .................................................................... 434
291 MSI-X_Capability Identifier Register - MSI-X_Cap_ID.................................................. 435
292 MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr........................................... 436
293 MSI-X Message Control Register - MSI-X_MCR........................................................... 437
294 MSI-X Table Offset Register - MSI-X_Table_Offset...................................................... 438
295 MSI-X Pending Bit Array Offset Register - MSI-X_PBA Offset........................................ 439
296 MU MSI-X Control Register X — MMCRx .................................................................... 440
297 Inbound MSI Interrupt Pending Registers — IMIPR [0:3] ............................................. 441
298 SDMA Controller Unit Registers ................................................................................ 446
299 LocalToHost Destination Lower Address Register - L2H_DLAR....................................... 447
300 LocalToHost Destination Upper Address Register - L2H_DUAR ...................................... 447
301 LocalToHost Source Lower Address Register - L2H_SLAR............................................. 448
302 LocalToHost Byte Count Register - L2H_BCR.............................................................. 449
303 LocalToHost Interrupt Counter/Acknowledge Register - L2H_ICAR ................................ 450
304 LocalToHost Control/Status Register - L2H_CSR......................................................... 451
305 LocalToHost Byte Swap Control Register - L2H_BSCR.................................................. 452
306 HostToLocal Destination Lower Address Register - H2L_DLAR....................................... 452
307 HostToLocal Source Upper Address Register - H2L_SUAR............................................. 453
308 HostToLocal Source Lower Address Register - H2L_SLAR............................................. 453
309 HostToLocal Byte Count Register - H2L_BCR.............................................................. 454
310 HostToLocal Interrupt Counter/Acknowledge Register - H2L_ICAR ................................ 455
311 HostToLocal Control/Status Register - H2L_CSR......................................................... 456
312 HostToLocal Byte Swap Control Register - H2L_BSCR.................................................. 457
313 SGPIO Input Mapping ............................................................................................. 465
314 Example 1: Multiplexer Block Outputs for SGPIO Unit 0 in Direct LED Mode.................... 470
315 Example 2: Multiplexer Block Outputs for SGPIO Unit 1 in SGPIO Mode ......................... 470
316 SGPIO Unit 0 Multiplexer Block Outputs for Example 2 ................................................ 471
317 SGPIO Unit 1 Multiplexer Block Outputs for Example 2 ................................................ 471
318 SGPIO Unit 0 Pin Multiplexing .................................................................................. 472
319 SGPIO Unit 1 Pin Multiplexing .................................................................................. 473
320 SGPIO Memory-Mapped Rejecters ............................................................................ 474
321 SGPIO Interface Control Register x - SGICRx............................................................. 475
322 SGPIO Programmable Blink Register x - SGPBRx ........................................................ 476
323 SGPIO Start Drive Lower Register x — SGSDLRx ........................................................ 478
324 SGPIO Start Drive Upper Register x — SGSDURx........................................................ 480
325 SGPIO Serial Input Data Lower Register x - SGSIDLRx................................................ 482
326 SGPIO Serial Input Data Upper Register x - SGSIDURx ............................................... 483