Intel CONTROLLERS 413808 - Manual (Page 268)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
268 Order Number: 317805-001US
3.8.4 Byte Parity Checking and Generation
The ATU internal bus interface supports byte-wise parity protection on the internal bus.
This includes ADDP[4:0] and DATAP[15:0] on the address bus (A[35:0]) and the data
bus (D[127:0]) respectively.
For an outbound request the ATU check the address parity before claiming the request
on the internal bus. When an error occurs, the transaction is not claimed. The Data
parity information is captured off the internal bus and stored in the internal queues. At
the PCI Express interface, the parity information is checked as the data packet is
transferred on the link. When a parity error occurs, the packet is nullified by using the
End Bad marker and state is updated so corrective action can be taken when the packet
is replayed on the PCI Express link. Header parity errors, which can only occur in the
retry buffer, results in a malformed packet that is dropped by the component on the
other side of the link. Data parity errors results in the EP bit being set to notify the
target of the TLP that the data is corrupt.
For an inbound write request, the ATU computes and appends address parity and data
parity before placing the TLP in the inbound queues. When an ECRC violation is
detected the packet is treated as when an address parity error occurred and the entire
packet is dropped without forwarding it to the internal bus. When a poisoned TLP is
received the parity for the entire payload is inverted so that the internal bus target
detects bad parity on all bytes.
3.8.4.1 Parity Generation
Data parity signals include byte enables in the calculation. Table 133 lists data bits that
are used for parity calculation. Parity bits are calculated by bit XOR-ing the data bits as
shown in Table 133 . As an example, the parity calculation for the lowest order byte of
the data bus D[7:0] is calculated as follows:
Equation 12.DATAP0 = D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6]
XOR D[7] XOR WBE[0]
Table 133. Parity Generation
Address/Data Parity Bit Address/Data Bus Address/Data Parity Bit Address/Data Bus
ADDP4 A[35:32] DATAP9 D[79:72], WBE[9]
ADDP3 A[31:24] DATAP8 D[71:64], WBE[8]
ADDP2 A[23:16] DATAP7 D[63:56], WBE[7]
ADDP1 A[15:8] DATAP6 D[55:48], WBE[6]
ADDP0 A[7:0] DATAP5 D[47:40], WBE[5]
DATAP15 D[127:120], WBE[15] DATAP4 D[39:32], WBE[4]
DATAP14 D[119:112], WBE[14] DATAP3 D[31:24], WBE[3]
DATAP13 D[111:104], WBE[13] DATAP2 D[23:16], WBE[2]
DATAP12 D[103:96], WBE[12] DATAP1 D[15:8], WBE[1]
DATAP11 D[95:88], WBE[11] DATAP0 D[7:0], WBE[0]
DATAP10 D[87:80], WBE[10]