Intel CONTROLLERS 413808 - Manual (Page 602)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
602 Order Number: 317805-001US
10.7.15 Interrupt Steering Register 2 — INTSTR2
The Interrupt Steering Register 2 allows system designers to direct any of 32 internal
or external interrupt sources to either one of the two internal interrupt exceptions, FIQ
and IRQ.
When an interrupt is enabled with the INTCTL2 register, this register steers the
interrupt to an internal interrupt exception.
Table 397. Interrupt Steering Register 2 — INTSTR2
Bit Default Description
31 0
2
SRAM Memory Controller Unit Error Interrupt Steering
0 = Interrupt Directed to Internal IRQ
1 = Interrupt Directed to Internal FIQ
30 0
2
South Internal Bus Bridge Error Interrupt Steering
0 = Interrupt Directed to Internal IRQ
1 = Interrupt Directed to Internal FIQ
29:14 0
2
Reserved.
13 0
2
SRAM DMA Error Interrupt Steering
0 = Interrupt Directed to Internal IRQ
1 = Interrupt Directed to Internal FIQ
12 0
2
SRAM DMA Normal Interrupt Steering
0 = Interrupt Directed to Internal IRQ
1 = Interrupt Directed to Internal FIQ
11:03 0
2
Reserved.
02 0
2
Reserved.
01 0
2
Reserved.
00 0
2
Reserved.
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor
address
CP6, Page 5, Register 2