Intel CONTROLLERS 413808 - Manual (Page 514)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
514 Order Number: 317805-001US
8.3.1.2 Address Decode Blocks
Address Decode is performed for transactions from input North Internal Bus port to
determine if the SMCU should claim the transaction. The north internal bus port claims
transactions targeting the SRAM memory array space, and transactions targeting the
memory-mapped registers.
8.3.1.2.1 SRAM Memory Array Space
The SRAM Memory Array Space can be accessed from the north internal bus port and
the SRAM memory space is defined with the SRAM Base Address Registers (SBAR and
SBUAR).
8.3.1.2.2 Memory-Mapped Register Space
The SMCU PMMR memory space offset is +1500H to +157FH. The registers are detailed
in Section 8.6, “Register Definitions” on page 535 .
The Memory-mapped registers are only accessible from the north internal bus port.
8.3.1.2.3 North Internal Bus Port Address Decode
North internal bus transactions are decoded to determine if they address the SRAM
Memory space or the memory-mapped registers. If the transaction addresses the
SRAM Memory Space, the transaction is queued in the north internal bus port
transaction queue.
8.3.1.3 Memory Transaction Queues
There are one set of transaction queues for transactions which address the SRAM
Memory Space from the north internal bus.The transaction queues are located in each
respective unit.
8.3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ)
The NIBPTQ stores memory transactions from the north internal bus. The NIBPTQ
supports 16 read transactions, each with up to 32 bytes buffer. The NIBPTQ also
supports 16 posted write transactions up to 32 bytes each.
8.3.1.4 Configuration Registers
The Configuration Registers block contains all of the memory-mapped registers listed in
Section 8.6, “Register Definitions” on page 535 . These registers define the memory
subsystem connected to the 4138xx. The status registers indicate the current SMCU
status.
8.3.1.5 SRAM Control Block
The SRAM Control Block contains all functionality to process the SRAM data accesses
per the transactions issued by the SMARB. To process a transaction the SRAM Control
Block employs several sub-blocks. The sub-blocks include the SRAM State Machine and
Pipeline Queues, and Error Correction Logic.
8.3.1.5.1 SRAM State Machine and Pipeline Queues
Since the SMCU generates error correction codes based on the data, the SMCU is a
pipelined architecture. Pipelining also ensures acceptable AC timings to the memory
interfaces. The SRAM state machine pipelines SRAM memory operations for several
clocks.