3 master-aborts signaled by the atu as a target, 1 uncorrectable address errors, 2 internal bus master-abort – Intel CONTROLLERS 413808 User Manual
Page 110: Message110, Uncorrectable address errors, Internal bus master-abort
Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
110
Order Number: 317805-001US
2.7.5.2
Inbound Read Completion or Inbound Configuration Write Completion
Message
The ATU encounters this error only in the PCI-X mode.
A master abort is signaled when the target of the transaction does not assert
DEVSEL#
within 7 clocks of the assertion of
FRAME#
.
When the ATU is signaled a Master-Abort while initiating either a Split Read Completion
Transaction or a Split Write Completion Message, the ATU discards the Split Completion
and take no further action.
2.7.5.3
Master-Aborts Signaled by the ATU as a Target
2.7.5.3.1
Uncorrectable Address Errors
The ATU can only signal this error during an Uncorrectable Address Error in the
Conventional mode.
Please see
Section 2.7.1, “Uncorrectable Address and Uncorrectable Attribute Errors on
for details on the ATU response to an Uncorrectable
Address Error in the Conventional mode.
2.7.5.3.2
Internal Bus Master-Abort
The ATU can only signal this error during an internal bus master abort in the PCI-X
mode.
Please see
Section 2.7.9.1, “Master Abort on the Internal Bus” on page 115
for details
on the ATU response to an Internal Bus Master Abort in the PCI-X mode.