Intel CONTROLLERS 413808 - Manual (Page 533)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 533
SRAM Memory Controller—Intel
®
413808 and 413812
8.4.2 Multi-bit Error Detection
If a multi-bit error occurs during a read or write transaction and error reporting is
enabled, the SMCU sets SMCISR[0] which asserts an interrupt to the core. Upon
receiving an interrupt, the core knows the interrupt was caused by a multi-bit error by
polling the SELOG registers.
When SMCU detects a multi-bit error during a read cycle and ECC calculation is enabled
in the SECCR, the SMCU target aborts the transaction, indicating to the MCU port that
an unrecoverable error has been detected. When the SMCU port is the north internal
bus port, the north internal bus port notifies the internal bus initiator of a multi-bit
error by returning a target abort. The SMCU records the error type in SELOG and the
address in SECAR and SECUAR.
When SMCU detects a multi-bit error during a write
15
cycle and error reporting is
enabled in the SECCR, the SMCU records the first multi-bit error by programming
SELOG, SECAR and SECUAR. The SMCU generates new ECC with the data before
sending it on DQ[31:0] so the contents of memory after the read-modify-write cycle
will be corrupted with correct ECC.
If a second error occurs before software clears the first by resetting SMCISR[0], the
error is not logged but the SMCU carries out the action described in Table 348 .
It is the interrupt handler responsibility to decide how to handle this error condition and
clear the SMCISR.
15.Any error condition during a write cycle actually occurs while performing the read portion of a
read-modify-write on a partial write. See Section 8.3.3.1, “ECC Generation” on page 520 for
details.