1 i2c control register x - icrx, 471 i, Section 14.8.1, “i2c control register x — icrx – Intel CONTROLLERS 413808 User Manual
Page 715: C control register, Icrx, Table 471. i, C control register x — icrx (sheet 1 of 2), The 4138xx uses the bits in the i, C control register (icrx) to control the i, C unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
715
I
2
C Bus Interface Units—Intel
®
413808 and 413812
14.8.1
I
2
C Control Register
x —
ICRx
The 4138xx uses the bits in the I
2
C Control Register (ICRx) to control the I
2
C unit.
Table 471. I
2
C Control Register x — ICRx (Sheet 1 of 2)
Bit
Default
Description
31:16
0000H
Reserved
15
0
Fast Mode:
0 = 100 KBit/sec operation
1 = 400 KBit/sec operation
14
0
2
Unit Reset
:
0 = No reset.
1 = Reset the I
2
C unit only.
13
0
2
Slave Address Detected Interrupt Enable
:
0 = Disable interrupt.
1 = Enables I
2
C unit to interrupt the 4138xx
upon detecting a slave address match or a general call
address.
12
0
2
Arbitration Loss Detected Interrupt Enable
:
0 = Disable interrupt.
1 = Enables the I
2
C unit to interrupt the 4138xx
upon losing arbitration while in master mode.
11
0
2
Slave STOP Detected Interrupt Enable
:
0 = Disable interrupt.
1 = Enables I
2
C unit to interrupt the 4138xx
when it detects a STOP condition in slave mode.
10
0
2
Bus Error Interrupt Enable
:
0 = Disable interrupt.
1 = Enables the I
2
C unit to interrupt the 4138xx
for the following I
2
C bus errors:
• As a master transmitter, no Ack was detected after a byte was sent.
• As a slave receiver, the I
2
C unit generated a Nack pulse.
Note:
Software is responsible for insuring that misplaced START and STOP conditions do not occur.
See
Section 14.6, “Glitch Suppression Logic” on page 712
09
0
2
IDBR Receive Full Interrupt Enable
:
0 = Disable interrupt.
1 = Enables I
2
C unit to interrupt the 4138xx
when IDBR has received a data byte from the I
2
C bus.
08
0
2
IDBR Transmit Empty Interrupt Enable
:
0 = Disable interrupt.
1 = Enables the I
2
C unit to interrupt the 4138xx
after transmitting a byte onto the I
2
C bus.
07
0
2
General Call Disable
:
0 = Enables the I
2
C unit to respond to general call messages.
1 = Disables I
2
C unit response to general call messages as a slave.
This bit must be set when sending a master mode general call message from the I
2
C unit.
06
0
2
I
2
C
Unit Enable
:
0 = Disables the unit and does not master any transactions or respond to any slave transactions.
1 = Enables the I
2
C unit (defaults to slave-receive mode).
Software must insure the I
2
C bus is idle before setting this bit.
05
0
2
SCL Enable
:
0 = Disables the I
2
C unit from driving the
SCL
line.
1 = Enables the I
2
C clock output for master mode operation.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Unit #
0
1
2
Intel XScale
®
processor internal bus address
offset
+2500H
+2520H
+2540H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible