Intel CONTROLLERS 413808 - Manual (Page 193)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 193
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.56 PCI-X Status Register - PCIXSR
This register identifies the capabilities and current operating mode of ATU when
operating in the PCI-X mode.
Table 83. PCI-X Status Register - PCIXSR (Sheet 1 of 2)
Bit Default Description
31:30 00
2
Reserved
29 0
2
Received Split Completion Error Message - This bit is set when the device receives a Split Completion
Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software
writes a 1 to this location.
0 = no Split Completion error message received.
1 = a Split Completion error message has been received.
28:26 001
2
Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting
of the Maximum Memory Read Byte Count field of the PCIXCMD register:
DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting
1 16 512 (Default)
2 32 1024
2 32 2048
2 32 4096
25:23 011
2
Designed Maximum Outstanding Split Transactions - The 4138xx can have up to four outstanding split
transactions.
22:21 01
2
Designed Maximum Memory Read Byte Count - The 4138xx can generate memory reads with byte
counts up to 1024 bytes.
20 1
2
4138xx is a complex device.
19 0
2
Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device’s
Requester ID is received. Once set, this bit remains set until software writes a 1 to this location.
0 = no unexpected Split Completion has been received.
1 = an unexpected Split Completion has been received.
18 0
2
Split Completion Discarded - This bit is set when the device discards a Split Completion because the
requester would not accept it. See Section 5.4.4 of the PCI-X Protocol Addendum to the PCI Local Bus
Specification, Revision 2.0 for details. Once set, this bit remains set until software writes a 1 to this
location.
0 = no Split Completion has been discarded.
1 = a Split Completion has been discarded.
Note: The 4138xx never sets this bit since there is no Inbound address responding to Inbound Read
Requests with Split Responses (Memory or Register) that has “read side effects.”
17 1
2
4138xx is a 133 MHz capable device.
16 32BITPCI#
4138xx can be configured to identify the add-in card to the system as 64-bit or 32-bit wide via a
user-configurable strap ( 32BITPCI# ). This strap, by default, identifies the 4138xx subsystem as 64-bit
unless the user attaches the appropriate pull-down resistor to the strap.
0 = The bus is 32 bits wide.
1 = The bus is 64 bits wide.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
rv
rv
rv
rc
rc
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rc
rc
ro
ro
ro
ro
ro
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+0D4H