64pci express slot capabilities register - pe_scap, Intel, Bit default description – Intel CONTROLLERS 413808 User Manual
Page 350
Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
350
Order Number: 317805-001US
3.17.64 PCI Express Slot Capabilities Register - PE_SCAP
This register identifies PCI Express slot specific capabilities.
Table 204. PCI Express Slot Capabilities Register - PE_SCAP
Bit
Default
Description
31:19
0000H
Physical Slot Number
This filed indicates the physical slot number attached to the Port. The hardware initialized value must be
assigned a slot number that is globally unique within the chassis. These registers should be initialized to
0 for ports connected to devices that are integrated on the system board.
18:17
00b
Reserved
16:15
00b
Slot Power Limit Scale
14:7
00H
Slot Power Limit Value
6
0
Hot-Plug Capable
5
0
Hot-Plug Surprise
4
0
Power Indicator Present
3
0
Attention Indicator Present
2
0
MRL Sensor Present
1
0
Power Controller Present
0
0
Attention Button Present
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
rv
rw
rv
rw
rv
rw
rv
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
pr
pr
pr
pr
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+0E4H