Intel CONTROLLERS 413808 - Manual (Page 104)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
104 Order Number: 317805-001US
2.7.3.9 Inbound Configuration Write Request
As a target, the ATU may encounter this error when operating in the Conventional or
PCI-X modes.
2.7.3.9.1 Conventional PCI Mode
To allow for correct data parity calculations for delayed write transactions, the ATU
delays the assertion of STOP# (signalling a Retry) until PAR is driven by the master. A
parity error during a delayed write transaction (inbound configuration write cycle) can
occur in any of the following parts of the transactions:
• During the initial Delayed Write Request cycle on the PCI bus when the ATU latches
the address/command and data for delayed delivery to the internal configuration
register.
• During the Delayed Write Completion cycle on the PCI bus when the ATU delivers
the status of the operation back to the original master.
The 4138xx ATU PCI interface has the following responses to a delayed write parity
error for inbound transactions during Delayed Write Request cycles with the given
constraints:
• When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY#
(disconnects with data) and two clock cycles later asserts PERR# notifying the
initiator of the parity error. The delayed write cycle is not enqueued and forwarded
to the internal bus.
• When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the
transaction by asserting STOP# and enqueues the Delayed Write Request cycle to
be forwarded to the internal bus. PERR# is not asserted.
• The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit,
additional actions are taken:
— When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear,
set the Detected Parity Error bit in the ATUISR. When set, no action.
• For PCI-X Mode 2, update the “ECC Control and Status Register - ECCCSR” on
page 195 , the “ECC First Address Register - ECCFAR” on page 198 , the “ECC
Second Address Register - ECCSAR” on page 199 , and the “ECC Attribute Register -
ECCAR” on page 200 for the transaction.
For the original write transaction to be completed, the initiator retries the transaction
on the PCI bus and the ATU returns the status from the internal bus, completing the
transaction.
For the Delayed Write Completion transaction on the PCI bus where a data parity error
occurs and therefore does not agree with the status being returned from the internal
bus (i.e. status being returned is normal completion) the ATU performs the following
actions with the given constraints:
• When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY#
(disconnects with data) and two clocks later asserts PERR# . The Delayed
Completion cycle in the IDWQ remains since the data of retried command did not
match the data within the queue.
• The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit,
additional actions are taken:
— When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear,
set the Detected Parity Error bit in the ATUISR. When set, no action.