Intel CONTROLLERS 413808 - Manual (Page 500)

Intel
®
413808 and 413812—System Controller (SC) and Internal Bus Bridge
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
500 Order Number: 317805-001US
19 0
2
Application DMA Group Control — this bit controls the Application DMA Initiators. The ADMA address
initiators are not granted the south internal address bus when this bit is set.
0 = Enabled
1 = Disabled
18 0
2
ATU-X Control — this bit controls the ATU-X. The ATU-X address initiator is not granted the south
internal address bus when this bit is set.
0 = Enabled
1 = Disabled
17 0
2
ATU-E Control — this bit controls ATU-E. The ATU-E address initiator is not granted the south internal
address bus when this bit is set.
0 = Enabled
1 = Disabled
16 0
2
SMBus Group Control — this bit controls the SMBus and PMON initiators. The SMBus and PMON
address initiators are not granted the south internal address bus when this bit is set.
0 = Enabled
1 = Disabled
15:03 000H Reserved.
02 0
2
Reserved.
01 0
2
XSC coreID1 control — this bit controls coreID1. The Intel XScale ® processor with coreID1 address
initiator is not granted the north internal address bus when this bit is set.
0 = Enabled
1 = Disabled
00 0
2
XSC coreID0 control — this bit controls coreID0. The Intel XScale ® processor with coreID0 address
initiator is not granted the north internal address bus when this bit is set.
0 = Enabled
1 = Disabled
Table 334. Internal Bus Arbitration Control Register — IBACR (Sheet 2 of 2)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
South XBG
internal bus address offset
+1640H