Intel CONTROLLERS 413808 - Manual (Page 579)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 579
Interrupt Controller Unit—Intel
®
413808 and 413812
10.5.4 High-Priority Interrupt (HPI#)
The HPI# pin generates an interrupt for implementation of critical interrupt routines.
10.5.5 Timer Interrupts
Each of the two timer units has an associated interrupt. Timer interrupts are connected
directly to the 4138xx interrupt controller and are posted in either the IINTSRC[3:0] or
FINTSRC[3:0] registers. These interrupts are set up through the timer control registers
described in Chapter 11.0, “Timers.”
10.5.6 Inter-Processor Interrupts
Note: IPIs are not supported on 4138xx.
10.5.7 Intel XScale
®
Processor Interrupts
The Intel XScale
®
processor can generate two type of interrupts that are routed from the
core as outputs and into the 4138xx ICU. This mechanism allows these two core interrupts
to be handled like any other peripheral interrupts by the ICU. For example, these interrupts
can be masked when desired using the INTCTLx registers and steered to either IRQ or FIQ
using the INTSTRx registers. The Intel XScale
®
processor PMU interrupt is generated
when the Intel XScale
®
processor PMU detects an overflow of one of its counters. The
Intel XScale
®
processor Cache interrupt is generated when the Intel XScale
®
processor
L2 cache detects a single bit ECC error. This interrupt can be used by software wishing to scrub memory when
a single-bit ECC error is detected. Refer to the
Intel XScale
®
processor External Architecture
Specification for more detailed descriptions on these interrupts.
10.5.8 Software Interrupts
The application program may use the SWI instruction to request interrupt service.