Intel CONTROLLERS 413808 - Manual (Page 82)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
82 Order Number: 317805-001US
2.5 Expansion ROM Translation Unit
The inbound ATU supports one address range (defined by a base/limit register pair)
used for the Expansion ROM. Refer to the PCI Local Bus Specification, Revision 2.3 for
details on Expansion ROM format and usage.
During a powerup sequence, initialization code from Expansion ROM is executed once
by the host processor to initialize the associated device. The code can be discarded
once executed. Expansion ROM registers are described in Section 2.14.37 through
Section 2.14.39 .
The inbound ATU supports an inbound Expansion ROM window which works like the
inbound translation window. A read from the expansion ROM windows is forwarded to
the internal bus. The address translation algorithm is the same as the inbound
translation; see Section 2.2.1.1, “Inbound Address Translation” on page 56 . As a PCI
target, the Expansion ROM interface behaves as a standard ATU interface and is
capable of returning a 64-bit access by the assertion of ACK64# in response to a
64-bit request.
The Expansion ROM unit uses the ATU inbound transaction queue and the inbound read
data queue.
When operating in the conventional PCI mode, the address of the inbound delayed read
cycle is entered into the ITQ queue and the delayed read completion data is returned in
the IRQ. That is, inbound reads to the Expansion ROM window are handled as delayed
transactions on the PCI bus.
When operating in the PCI-X mode, the address of the inbound read cycle is entered
into the ITQ queue and the read completion data is returned in the IRQ. That is,
inbound reads to the Expansion ROM window are handled as split transactions on the
PCI bus. The internal bus initiator interface fills the IRQ read queue with the full byte
count before generating the split completion transaction on the PCI bus. That is, the
ATU generates a Read request on the internal bus with byte count set to the byte count
specified in the PCI read. The PBI (Flash Interface) returns data in:
• either one or more 1024 byte split completion transactions when byte count is
greater than or equal to 1024 bytes or
• one split completion with the full byte count when byte count is less than 1024
bytes.
Expansion ROM writes are not supported and result in a Target Abort.