Intel CONTROLLERS 413808 - Manual (Page 679)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 679
UARTs—Intel ® 413808 and 413812
3 0
2
Interrupt Enable (IE): Global control all UART interrupts.
0 = interrupts disabled.
1 = interrupts enabled.
NOTE: This bit is not valid when in Loopback mode.
2 0
2
Preserved.
1 0
2
Request to Send (RTS):
Non-Autoflow mode: When not in Autoflow mode (AFE bit of MCR is clear), this bit
controls the Request-to-Send (RTS#) output pin.
0 = RTS# pin is 1
1 = RTS# pin is 0
Autoflow mode: When in Autoflow mode (AFE bit of MCR is set), auto-RTS is
enabled. RTS# behaves as follows:
• Auto-RTS disabled. Autoflow works only with auto-CTS.
• Auto-RTS enabled. Autoflow works with both auto-CTS and auto-RTS.
0 0
2
Reserved
Table 454. UART x Modem Control Register - (UxMCR) (Sheet 2 of 2)
Bit Default Description
PC
I
IO
P
A
tt
ri
bu
te
s
A
tt
ri
bu
te
s
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
pr
na
rw
na
rv
na
Unit #
01
Intel XScale ® Core internal bus address
+2310H (DLAB=x)
+2350H (DLAB=x)
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible