Intel CONTROLLERS 413808 - Manual (Page 78)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
78 Order Number: 317805-001US
2.3 Big Endian Byte Swapping
Each memory and I/O window has an associated byte swapping enable located in the
following address translation registers:
• bit 0 of Inbound Address Translate Value Register 0-3 (IATVR0-3)
• bit 0 of Inbound Expansion ROM Translate Value Register (ERTVR)
• bit 0 of Outbound I/O Window Translate Value Register (OIOWTVR)
• bit 27 of Outbound Upper Memory BAR 0-3 (OUMBAR0-3)
Note: The Messaging Unit (MU) Memory is mapped in PCI Window 0 (ATU Base Address
Register 0) along with the MSI-X table structures. Byte swapping should not be enabled
for BAR0 when using MSI-X.
2.3.1 Inbound Byte Swapping
When enabled, the swapping occurs as described in Figure 9, “Inbound Byte Swapping
for 32-bit PCI” on page 78 and Figure 10, “Inbound Byte Swapping for 64-bit PCI” on
page 78 . The bytes are swapped within a DWORD and byte swapping is performed for
all transactions regardless of byte count.
Figure 9. Inbound Byte Swapping for 32-bit PCI
Figure 10. Inbound Byte Swapping for 64-bit PCI
Byte 0 Byte 0
Word 0 [31:24] Word 0 [23:16] Word 0 [15:8] Word 0 [7:0]
Word 0 [7:0] Word 0 [15:8] Word 0 [23:16] Word 0 [31:24]
32-Bit Word on Internal Data Bus
32-Bit Word on PCI Bus
+3 +2 +1 +0
B6189-01
+7 +6 +5 +4 +3 +2 +1 +0
Byte A Byte B Byte C Byte D
Word 1 [7:0] Word 1 [15:8] Word 1 [16:23] Word 1 [31:24]
Two 32-Bit Words on
Internal Data Bus
Two 32-Bit Words
on 64-Bit PCI Bus
Word 0 [31:24] Word 0 [23:16] Word 0 [15:8] Word 0 [7:0]
Word 0 [7:0] Word 0 [15:8] Word 0 [23:16] Word 0 [31:24]
Byte A Byte B Byte C Byte D Word 1 [31:24] Word 1 [23:16] Word 1 [15:8] Word 1 [7:0]
B6190-01