Intel CONTROLLERS 413808 - Manual (Page 136)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
136 Order Number: 317805-001US
Table 25 describes the bus mode and frequency initialization pattern that the ATU
signals on its secondary bus when coming out of P_RST# , after having evaluated the
above information.
When operating in Central Resource Mode (PCIX_EP# = 1), the PCI-X initialization
pattern is driven directly from the PCI-X capability field (bits 19:16) in the “PCI
Configuration and Status Register - PCSR” . The default value of this field is determined
by the PCIX_EP# , PCIXM1_100# , PCIXM2_100# straps, as well as the P_MODE2 ,
P_PCIXCAP , and P_M66EN , signals as described in Table 24, “PCI Bus Frequency
Initialization” on page 135 .
While P_RSTOUT# is asserted the initialization pattern is driven on the PCI bus.
Software can override the default pattern by writing a new value to PCSR[19:16],
before clearing the Central Resource PCI Bus Reset field (bit 21) in the “PCI
Configuration and Status Register - PCSR” .
When P_RSTOUT# is asserted any time after initial power on, software must enforce
the 1ms reset assertion time (T
rst
) required in the PCI specifications.
When operating as an endpoint ( PCIX_EP# = 0), PCSR[19:16] contains the
initialization pattern captured off the bus during P_RST# .
Table 25. PCI-X Initialization Pattern
PERR# DEVSEL# STOP# TRDY# Mode
a
a. 4138xx supports neither PCI-X 533 Mode nor ECC in Mode 1.
Clock Period
(Ns)
Clock Frequency
(MHz)
Maxim
um
Minimu
m
Minimu
m
Maxim
um
Deasserted Deasserted Deasserted Deasserted
PCI 33
60
30 16 33
PCI 66 30 15 33 66
Deasserted Deasserted Deasserted Asserted
PCI-X
Mode 1
20 15 50 66
Deasserted Deasserted Asserted Deasserted
PCI-X
Mode 1
15 10 66 100
Deasserted Deasserted Asserted Asserted
PCI-X
Mode 1
10 7.5 100 133
Deasserted Asserted Deasserted Deasserted
PCI-X
Mode 1
Reserved
Deasserted Asserted Deasserted Asserted
PCI-X
Mode 1
Deasserted Asserted Asserted Deasserted
PCI-X
Mode 1
Deasserted Asserted Asserted Asserted
PCI-X
Mode 1
Asserted Deasserted Deasserted Deasserted PCI-X 266
(Mode 2)
Asserted Deasserted Deasserted Asserted
PCI-X 266 b
(Mode 2)
b. The P_CLK[3:0] frequency and associated initialization pattern in PCI-X 266 mode for is selected in the
“PCI
Configuration and Status Register - PCSR” on page 178 .
20 15 50 66
Asserted Deasserted Asserted Deasserted PCI-X 266
(Mode 2)
15 10 66 100
Asserted Deasserted Asserted Asserted
PCI-X 266
(Mode 2)
10 7.5 100 133
Asserted Asserted Deasserted Deasserted PCI-X
Reserved
Asserted Asserted Deasserted Asserted PCI-X
Asserted Asserted Asserted Deasserted PCI-X
Asserted Asserted Asserted Asserted PCI-X