Intel CONTROLLERS 413808 - Manual (Page 432)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
432 Order Number: 317805-001US
4.7.23 Message Address Register - Message_Address
The Message address register specifies the DWORD aligned address for the MSI
memory write transaction. The value is set by system software during initialization.
Note: Refer to the Peripheral Registers Chapter for the default internal bus address. This
register is part of the configuration space of the Address Translation Unit that is setup
as an endpoint.
Table 288. Message Address Register - Message_Address
Bit Default Description
31:2 00000000H Message Address - DWORD aligned Message Address. This value is set by system software.
1:0
002
Reserved.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
PCI Configuration Offset
A4H
Internal Bus Address Offset
0A4H