Intel CONTROLLERS 413808 - Manual (Page 131)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 131
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.11.2 PCI-X Interface Status Reporting
The following registers are located in the configuration space header and extended
space and provide status (error conditions) of the PCI Interface.
Note: Registers or bits within a register that are described in Table 20 and Table 21 exist in
each function independently.
Table 21. PCI-X Host Interface Status Reporting Usage
a
a. This table is referring to only enabled functions. And in root complex mode multi-function is not applicable.
Register Name Register Bits Description Usage
ATU Status Register - ATUSR
Bit 15 - Detected Parity Error
Address and Attribute parity error is
reported to all functions
simultaneously.
Data parity error is reported to only
the function involved.
Bit 14 - SERR# Asserted
SERR# Asserted is reported to only
the function involved.
Bit 13 - Master Abort
Master Abort is reported to only the
function involved.
Bit 12 - Target Abort (Master) Target Abort (Master) is reported to
only the function involved.
Bit 11 - Target Abort (Target) Target Abort (Target) is reported to
only the function involved.
Bit 8 - Bit Master Parity Error Master Parity Error is reported to only
the function involved.
ATU PCI-X Status Register - PCIXSR
Bit 29 - Received Split
Completion Error Message
Received Split Completion Error
Message is reported to only the
function involved.
Bit 19 - Unexpected Split
Completion
Unexpected Split Completion is
reported to only the function
involved.
Bits[15:8] - Bus Number
Bits[7:3] - Device Number
Bits[2:0]
Each function indicates its function
number.
ATU ECC Control and Status Register -
ECCCSR
Bits[27:2]
Address and Attribute ECC error is
reported to all functions
simultaneously.
Data ECC error is reported to only
the function involved.