Intel CONTROLLERS 413808 - Manual (Page 47)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 47
Introduction—Intel
®
413808 and 413812
1.5.13 Internal Bus System Controller
Each internal bus (north and south) employs a internal System Controller. The internal
System Controller observes all the address or data bus request from requestors and
completors connected to the internal bus. The internal System Controller includes
features to handle: internal address bus arbitration, internal data bus arbitration,
framing Address bus cycles, framing Data bus cycles, and provides the shared address
and shared data paths from/to units.
1.5.14 Inter-Processor Communication
All intern processor communications on the 4138xx are over the internal bus.
1.5.15 Inter-Processor Messaging Unit
The IPMU is not available on the 4138xx.
1.5.16 Timers
The 4138xx supports two programmable 32-bit timers per processor. The 4138xx also
supports one watchdog timer per processor.
1.5.17 GPIO
The 4138xx includes sixteen General Purpose I/O (GPIO) pins.
1.5.18 FSENG
The FSENG block contains the Serial-Attached SCSI(SAS) and SATA engines. The
81348 contains up to eight engines. And each engine is composed of the transport,
link, PHY and physical layers. This unit is for use by the Transport Firmware only.