Intel CONTROLLERS 413808 - Manual (Page 436)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
436 Order Number: 317805-001US
4.7.27 MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr
The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus
Specification, Revision 2.3. This register describes the location of the next item in the
function’s capability list. For the 4138xx, the next capability (PCI-X capability list) is
located at off-set E0H.
Note: Refer to the Peripheral Registers Chapter for the default internal bus address. This
register is part of the configuration space of the Address Translation Unit that is setup
as an endpoint.
Table 292. MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr
Bit Default Description
07:00 A0H
Next_ Item_ Pointer - This field provides an offset into the function’s configuration space pointing to the
next item in the function’s capability list which in the 4138xx is the MSI extended capabilities header.
PCI
IOP
Attributes
Attributes
7 4 0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
PCI Configuration Offset
B1H
Internal Bus Address Offset
480B1H