Intel CONTROLLERS 413808 - Manual (Page 488)

Intel
®
413808 and 413812—System Controller (SC) and Internal Bus Bridge
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
488 Order Number: 317805-001US
7.2.3 Parity Testing
The 4138xx supports parity protections on both the 36-bit address and 128-bit data
bus south internal bus. Parity is supported on a byte-wise basis. The SC provides
hardware test features that allows the user to force address or data parity errors on the
internal bus. This feature allows the user to test software error handling routines by
forcing an address or data parity error on the internal bus. Parity error is forced by
XORing (inverting) good parity bit or bits before they are driven on the bus. The
4138xx provides separate sets of error registers for injecting address bus and data bus
parity error. The 4138xx provides an address mask register and a data mask register.
The user can program the mask registers to select which parity bit(s) ought to be
inverted. 4138xx also provides a register that allows the programmer to select the
initiator of a given transaction by providing the ID of the initiator.
This register also provides an enable bit which must be set by software and is reset by
hardware. This provides a way of injecting an error only once — a one-shot process.
For example, error is injected only during the address cycle for an address parity test,
and during the first data cycle for a data parity test. Table 331 lists the Initiator IDs
that must be programmed in the Initiator ID field of SIBATCR for address parity testing
during address request. Table 331 lists the Initiator IDs that must be programmed in
the Initiator ID field of SIBDTCR for data parity testing during writes. Table 331 lists the
Initiator IDs that must be programmed in the Initiator ID field of SIBDTCR for data
parity testing during read completions.
The initiator in this context is used to identify the source of the address or data. For
example, when data parity error is to be injected while the DDR MCU is returning read
completion data, the DDR MCU Initiator ID must be used. However, when data parity
error is to be injected when the ATU is writing data to the DDR Memory, the ATU
Initiator ID must be used.
Figure 55. Typical Internal Bus System Controller Block Diagram
Agent A
Internal Bus
System Controller
ABG,
DBG
Address
to
SC
Data
to
SC
Address
to
Agent
Data
to
Agent
Signals
to
Agent
Agent B
ABG,
DBG
Signals
to
SC
Address
to
SC
Data
to
SC
Signals
to
SC
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